1. Field of the Invention
The present invention relates to a semiconductor integrated circuit testing apparatus for testing a semiconductor integrated circuit, and more particularly, relates to a semiconductor integrated circuit testing apparatus (generally referred to as IC tester) which can be suitably used in testing a semiconductor integrated circuit having a logic portion and a memory portion formed together on one chip, and to a method of controlling the semiconductor integrated circuit testing apparatus, which defines the sequence of operations of the testing apparatus.
2. Description of the Related Art
Heretofore, a semiconductor integrated circuit (hereinafter referred to as IC) is called, in this technical field, a memory IC or a logic IC. The memory IC is one in which a memory portion is dominant therein, and the logic IC is one in which a logical circuit portion (logic portion) is dominant therein. In addition, an IC having a logic portion and a memory portion formed together on one chip (also referred to as logic/memory mixed IC) is called a systematic LSI (Systematic Large Scale Integrated Circuit) or the like, and the ICs of this type tend to increase from now on. The characteristic of a systematic LSI is that the number of pins required for a logic portion is several times or so as large as the number of pins required for a memory portion. Therefore, in the case of testing a logic portion of such a systematic LSI, the number of ICs that can be simultaneously tested (commonly called the number of ICs to be simultaneously measured or the number of parallel measurements) is limited due to the large number of pins of the IC under test.
FIG. 7 shows a connecting relationship between an IC testing apparatus and ICs under test (hereinafter, referred to as DUTs) in the case that the DUTs are ICs each having a logic portion and a memory portion formed together on one chip. There are provided in the IC testing apparatus 10 many channels (signal paths) through which driving signals (test pattern signals, address signals, control signals and the like) are supplied to the DUTs. The number of DUTs to be simultaneously tested is determined depending on the total number of channels. FIG. 7 is a block diagram showing, by way of example, a connecting state in the case of testing two DUTs (DUT 1 and DUT 2) each having 256 pins by the IC testing apparatus 10 having total of 512 channels CH1 through CH512 that are channel 1 (CH1) through channel 512 (CH512). Each of the DUT 1 and the DUT 2 is assumed to be a logic/memory mixed IC having 64 pins from pin P1 until pin P64 as the pins for testing the memory portion, and 192 pins from pin P65 until pin P256 as the pins for testing logic portion.
In this case, 64 channels 11 from channel CH1 until channel CH64 of the IC testing apparatus 10 are connected to the pins P1 through P64 of the DUT1, respectively, and the 192 channels from channel CH65 through channel CH256 of the IC testing apparatus 10 are connected to the pins P65 through P256 of the DUT1, respectively. However in this case, since the memory portion must be also operated for testing the logic portion of the DUT 1, each of 256 channels 12 from channel CH1 through channel CH512 of the IC testing apparatus 10 is connected to corresponding one of the pins P1 through P256 of the DUT1 to perform the testing. Since the connecting relationship for the DUT 2 is quite similar to the case of the DUT 1, the explanation thereof will be omitted.
In this manner, since only two DUTs can be connected to the IC testing apparatus 10 under the above conditions, as shown in FIG. 7, two DUTs, namely, DUT 1 and DUT 2 are connected to the IC testing apparatus 10, and the logic portion and the memory portion of each of the DUT 1 and the DUT 2 are tested to determine whether they have any defect or not.
Incidentally, although the required number of pins of the memory portion is less than that of the logic portion, there is a characteristic that a time duration or length Mt required for testing the memory portion is longer than a time duration or length Lt required for testing the logic portion. For example, in the case of the DUTs 1 and 2 shown in FIG. 7, Mt is 60 seconds, while Lt is approximately 5 seconds or so. Therefore, in this case, it takes approximately 65 seconds for testing both of the logic portion and the memory portion. For example, in the case of testing 1000 DUTs of this type, the required time length for the testing is, as two DUTs can be connected to the IC tester 10 at the same time, (60+5)xc3x971000xc3x97256/512=65xc3x971000xc3x971/2=32500 seconds≈9 hours.
This value of 9 hours is a time length required for the test only, and in reality, there is necessary, in addition to the test, a sorting process for sorting the tested ICs into non-defective articles and defective articles is necessary. Therefore, the time length required for the sorting process must be added. Consequently, a longer test time is actually required. Further, assuming that the number of channels to be used for testing the logic portion of a DUT is Lch, and the total number of channels of the IC tester 10 is Tch, xe2x80x9c256/512xe2x80x9d in the above calculating formula corresponds to Lch/Tch. This is equal to the reciprocal of the number of DUTs that can be tested simultaneously.
As mentioned above, when ICs of mixed logic/memory are tested by one IC testing apparatus, there is a problem that the time length required for testing the ICs becomes long. For this reason, there may be employed a case that two IC testing apparatus are provided for testing the memory portions of the ICs of mixed logic/memory using one of the two IC testing apparatus, and for testing the logic portions of the ICs of mixed logic/memory using the other one of the two IC testing apparatus.
FIG. 8 shows a connecting relationship between an IC testing apparatus 10 and DUTs in the case that the only memory portions of the logic/memory mixed ICs are tested by the IC testing apparatus 10 shown in FIG. 7. In the case of testing the memory portions of the DUTs, it is sufficient that the IC testing apparatus 10 supplies the driving signals only to the pins for the memory portion of each DUT. As already explained with reference to FIG. 7, the total number of channels Tch of the IC testing apparatus 10 is 512, and the number of pins required for the memory portion of each DUT is 64 pins from P1 to P64. Therefore, 512/64=8 DUTs (DUT1, DUT2, DUT3, . . . , DUT8) can be connected to the IC testing apparatus 10. Consequently, the number of DUTs that can be connected to one IC testing apparatus is remarkably increased.
In this manner, in the case of testing the memory portion, the number of DUTs that can be simultaneously tested is eight.
Therefore, the time length required for testing, for example, 1000 DUTs is 60xc3x971000xc3x9764/512=7500 seconds. In this case, assuming that the number of channels to be used for testing the memory portion of a DUT is Mch, xe2x80x9c64/512xe2x80x9d corresponds to Mch/Tch. This is equivalent to the reciprocal of the number of DUTs that can be simultaneously tested.
When the logic portions of the 1000 DUTs are tested by the other one of the two IC testing apparatus (the connecting relationship is the same as that shown in FIG. 7), the test time duration is 5xc3x971000xc3x97256/512=2500 seconds. As a result, when the memory portions and the logic portions of the DUTs are separately tested by two IC testing apparatus, respectively, the total time length Ttim required for the test is 7500 seconds+2500 seconds=10000 seconds. When this time length is compared with the time length (32500 seconds) required in the test by one IC testing apparatus, it is recognized that there is an advantage in the two IC testing apparatus case that the required time length can be remarkably reduced. However, in this case, also the sorting process is necessary in each of the memory portion test and the logic portion test.
Assuming that the time length required for the sorting process is, in each case of the memory portion test and the logic portion test, one second per simultaneous test, the sorting time in the memory portion test is 1000xc3x9764/512=125 seconds, and the sorting time in the logic portion test is 1000xc3x97256/512=500 seconds. Therefore, the time length required for both sorting processes is 625 seconds. Consequently, the total time length from the test start to the test end is 7500+2500+125+500=10625 seconds.
As mentioned above, in the case of testing logic/memory mixed ICs, the time duration required for the test can remarkably be reduced if two IC testing apparatus be used. However, in this case, since two very expensive IC testing apparatus must be provided, there is a serious problem that an economic burden to a user is very much increased. As a result, there is a drawback in the case of using two IC testing apparatus that the cost required for testing logic/memory mixed ICs is considerably increased.
It is an object of the present invention to provide an IC testing apparatus that can reduce the time duration required for a testing, even if ICs under test are ones each having a logic portion and a memory portion formed together on one chip.
It is another object of the present invention to provide an IC testing apparatus that can efficiently test the logic portions and the memory portions of ICs each having a logic portion and a memory portion formed together, and hence can carry out a testing for the ICs of logic and memory portions within a shorter time duration than in the case of testing the same ICs using two IC testing apparatus.
In order to accomplish the above objects, in one aspect of the present invention, there is provided a semiconductor integrated circuit testing apparatus comprising: a semiconductor integrated circuit tester having a predetermined number of channels for supplying driving signals; IC sockets the number of which is the same as the number of memory portions of semiconductor integrated circuits that can be simultaneously tested by the tester, the number of IC sockets being determined depending on the number of the channels of the semiconductor integrated circuit tester and the number of channels required for testing a memory portion of a semiconductor integrated circuit to be tested; and a switching circuit connected between the IC sockets and the semiconductor integrated circuit tester, the switching circuit switching between a state in which driving signals for testing memory portions of semiconductor integrated circuits under test are supplied to all of said IC sockets and a state in which driving signals for testing a logic portion or portions of a semiconductor integrated circuit or. circuits under test are supplied to a part of said IC sockets.
In a preferred embodiment, the switching circuit includes switches the number of which is the same as the number of the channels of the semiconductor integrated circuit tester, and each of those switches is constituted by ON/OFF switches the number of which is equal to a value of quotient (integer portion thereof obtained by dividing the total number of pins of a semiconductor integrated circuit under test by the number of channels required for testing a memory portion of that semiconductor integrated circuit under test. One ends of the ON/OFF switches of each of the switches are connected in common to an associated one of the channels. In addition, the other ends of the ON/OFF switches are selectively connected to corresponding output lines.
The number of the IC sockets is equal to a value of quotient (integer portion thereof obtained by dividing the number of the channels of the semiconductor integrated circuit tester by the number of channels required for testing a memory portion of the semiconductor integrated circuit under test, and the number of semiconductor integrated circuits under test whose logic portions are tested is equal to a value of quotient (integer portion thereof) obtained by dividing the number of the channels of the semiconductor integrated circuit tester by the number of channels required for testing a logic portion of the semiconductor integrated circuit under test.
In another aspect of the present invention, there is provided a method of controlling the semiconductor integrated circuit testing apparatus described above, which comprises the steps of: (a) simultaneously testing, at a time point when a testing for logic portions of the half of semiconductor integrated circuits under test among semiconductor integrated circuits under test mounted on the IC sockets has been completed, the memory portions of all of the semiconductor integrated circuits under test;
(b) starting, at a time point when the testing for the memory portions has been completed, a testing for logic portions of the remaining half of the semiconductor integrated circuits under test among the semiconductor integrated circuits under test; (c) first exchanging, during the testing for the logic portions of the remaining half of the semiconductor integrated circuits under test, the first half of the semiconductor integrated circuits whose logic portions and memory portions have been tested for semiconductor integrated circuits to be tested next; (d) starting a testing for the logic portions of the exchanged semiconductor integrated circuits under test at a time point when the testing for the logic portions of the remaining half of the semiconductor integrated circuits under test has been completed, and secondly exchanging, during the testing for the logic portions of the exchanged semiconductor integrated circuits under test, the remaining half of the semiconductor integrated circuits under test whose logic portions and memory portions have been tested for semiconductor integrated circuits to be tested next; and (e) simultaneously testing, after the secondly exchanging step, at a time point when the testing for the logic portions of the semiconductor integrated circuits under test exchanged in the first exchanging step has been completed, the memory portions of all of the semiconductor integrated circuits under test exchanged in the first and second exchanging steps, and whereby semiconductor integrated circuits can be tested substantially with no idle time by repeating the steps (b) to (e).
According to the above controlling method, when the memory portions are tested, channels the number of which is equal to the number required for the testing of the memory portions are connected to all of the IC sockets, and the memory portions of the ICs under test mounted on all of the IC sockets are simultaneously tested by supplying the driving signals to the IC sockets.
In addition, when the logic portions are tested, channels the number of which is equal to the number required for the testing of the logic portions are connected only to a part of the IC sockets, and the logic portions of the ICs under test mounted on the part of the IC sockets are tested by supplying the driving signals thereto.
When the testing has been completed, the logic portions of the ICs under test mounted on an another part of the IC sockets are tested by supplying the driving signals to those IC sockets. By repeating those operations, the logic portions of the ICs under test mounted on all of the IC sockets are tested.
Therefore, according to the present invention, when ICs under test are mounted on all of the IC sockets the number of which is the same as the number of memory portions that can be tested simultaneously, the memory portions of all of the ICs under test can be tested simultaneously. In addition, the logic portions are tested by repeating the testing for the logic portions that can be tested simultaneously. As a result, the memory portions and the logic portions of the ICs under test can be tested within the time duration substantially equal to or shorter than that in the case that two IC testing apparatus are used for the testing of the same ICs.